Reading Zilog S8000 QIC Tapes (MFM format)

I've read a few tapes purportedly from the Zilog S8000 using a DEI drive, and a quick look at the data captures in the Saleae GUI appears to show an MFM format, but with the data block anatomy unknown at this time.

So that I can orient myself to the data pulses I see in these captures, I'm reviewing the 

DEI (Data Electronics Incorporated) Series CMTD-3400S2 6400 BPI High Density Cartridge Magnetic Tape Drive Operation and Maintenance Manual

It is believed that this is the drive that these tapes were written with.

Here's what the beginning of the first block looks like:

TRACK ORDER

First, we find the track order, which is 3, 2, 1, 4.  This is the same order on the physical from top-to-bottom as the Kennedy 64XX format, except that this manual calls the first track "Track 1", where all other drives I've seen refer to the first track as "Track 0"

From the Series CMTD-3400S2 Operation and Maintenance Manual, Page 3-2

DATA BLOCK ANATOMY

Now I'm hunting for the data block anatomy, like I show in my QIC-11, QIC-24, and Kennedy 64XX formats, but I can't find anything similar.

Here's the closest  I can come:

From the Series CMTD-3400S2 Operation and Maintenance Manual, Page 4-9

RDS must stand for Read Data Strobe:

From the Series CMTD-3400S2 Operation and Maintenance Manual, Page 3-9

From the Series CMTD-3400S2 Operation and Maintenance Manual, Page 4-2

INTER-BLOCK GAPS?

We can see inter-block gaps, but is this referenced in the manual?

CRC:

05/09/2016:

Mattis:

[In the context of reverse-engineering the CRC from the physical drive hardware]

I checked the controller board and it wasn't long until I found that the read data signal (RNZ-) goes almost directly into a Signetics N9401 chip, just after passing a 74LS240 receiver.

Page 240 in the 1984 Signetics Bipolar LSI Data Manual 

It is an integrated CRC generator/checker. There are two on the board. I presume one is for READ and the other for WRITE. The chip has configurable polynomials and are set to use X^16 + X^15  + X^2 + 1. P=8005

The P and CWE are held high, while the MR (Master Reset) signal is controlled by some logic. My guess is that the MR is activated either at every block or at start of tape. MR will then set the internal shift register to 0.

So what this knowledge I will experiment in which way the bits enter the shift register and see if I can get a match.

More to come as I progress...